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EM78P451S
8-Bit Microcontroller with OTP ROM
Product Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
June 2004
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.
Copyright (c) 2005 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8223 Fax: +1 408 366-8220
Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com
Shanghai: Elan Microelectronics Shanghai Corporation, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 021 5080-3866 Fax: +86 021 5080-4600
Contents
Contents
1 2 3 4 GENERAL DESCRIPTION................................................................................................... 1 FEATURES........................................................................................................................... 1 PIN ASSIGNMENT ............................................................................................................... 2 FUNCTION DESCRIPTION.................................................................................................. 4 4.1 Operational Registers ..................................................................................................4
4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 4.1.10 4.1.11 4.1.12 4.1.13 4.1.14 4.1.15 R0 (Indirect Address Register) ...................................................................................... 4 R1 (TCC) ....................................................................................................................... 4 R2 (Program Counter) & Stack...................................................................................... 4 R3 (Status Register) ...................................................................................................... 6 R4 (RAM Select Register) ............................................................................................. 6 R5~R8 (Port 5 ~ Port8).................................................................................................. 7 R9 (Port9) ...................................................................................................................... 7 RA (SPIRB: SPI Read Buffer)........................................................................................ 8 RB (SPIWB: SPI Write Buffer)....................................................................................... 8 RC (SPIS: SPI Status Segister)..................................................................................... 8 RD (SPIC: SPI Control Register)................................................................................... 9 RE (TMR1: Timer1 register) ........................................................................................ 10 RF (PWP: Pulse width preset register)........................................................................ 10 R20~R3E (General Purpose Register)........................................................................ 10 R3F (Interrupt Status Register) ................................................................................... 10 A (Accumulator) ........................................................................................................... 10 CONT (Control Register) ............................................................................................. 11 IOC5 ~ IOC9 (I/O Port Control Register)..................................................................... 11 IOCC (T1CON: Timer1 control register) ...................................................................... 11 IOCD (Pull-high Control Register) ............................................................................... 12 IOCE (WDT Control Register) ..................................................................................... 12 IOCF (Interrupt Mask Register) ................................................................................... 13
4.2
Special Purpose Registers .........................................................................................10
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7
4.3 4.4 4.5
TCC/WDT Presacler ..................................................................................................14 I/O Ports .....................................................................................................................15 SERIAL PERIPHERAL INTERFACE MODE..............................................................17
4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 Overview & Features ................................................................................................... 17 SPI Function Description ............................................................................................. 19 SPI Signal & Pin Description ....................................................................................... 20 Programmed the related registers............................................................................... 22 SPI Mode Timing ......................................................................................................... 24 Software Application of SPI ......................................................................................... 25 Overview...................................................................................................................... 30 Function description .................................................................................................... 30
* iii
4.6
Timer 1 .......................................................................................................................30
4.6.1 4.6.2
Product Specification (V1.0) 06.01.2004
Contents
4.6.3
Programmed the related registers............................................................................... 30
4.7 4.8 4.9
RESET and Wake-up .................................................................................................31 Interrupt......................................................................................................................37 Oscillator ....................................................................................................................38
4.9.1 4.9.2 4.9.3 Oscillator Modes.......................................................................................................... 38 Crystal Oscillator/Ceramic Resonators (XTAL) ........................................................... 38 RC Oscillator Mode ..................................................................................................... 40
4.10 Code Option Register.................................................................................................41 4.11 Instruction Set ............................................................................................................42 5 6 4.12 Timing Diagrams ........................................................................................................45 ABSOLUTE MAXIMUM RATING ....................................................................................... 46 ELECTRICAL CHARACTERISTICS.................................................................................. 46 6.1 7 DC Characteristic .......................................................................................................46 6.2 AC Characteristic .......................................................................................................47 Application Circuit ............................................................................................................ 48
APPENDIX
A B Package Types .................................................................................................................. 49 Package Information......................................................................................................... 49
Specification Revision History
Doc. Version 1.0 Revision Description Initial version Date 06/01/2004
iv *
Product Specification (V1.0) 06.01.2004
EM78P451S
8-Bit Microcontroller with OTP ROM
1
GENERAL DESCRIPTION
The EM78P451S is an 8-bit microprocessor designed and developed with low-power, high speed CMOS technology. Its operational kernel is implemented with RISC-like architecture and is available in the mask ROM version. The one time programmable (OTP) version is flexible, both in mass production or engineering test stages. OTP provide users with unlimited volume with favorable price opportunities. This device is equipped with the Serial Peripheral Interface (SPI) function. The EM78P451S is very suitable for wired communication. Only 58 easy-to-learn instructions are needed and user's program can be emulated with EMC In-Circuit Emulator (ICE).
2
FEATURES
Operating voltage range: 2.3V~5.5V. Operating temperature range: 0C~70C. Operating frequency range (base on 2 clocks ):
* * * *
Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.3V. RC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.3V.
Low power consumption: Less then 3 mA at 5V/4MHz Typically 10 A during sleep mode
Serial Peripheral Interface (SPI) available. 4K x 13 bits on chip ROM (EM78P451S). 11 special function registers. 140x 8 bits on chip general-purposed registers. 5 bi-directional I/O ports (35 I/O pins). 3 LED direct sinking pins with internal serial resistors. Built-in RC oscillator with external serial resistor, 10% variation. Built-in power-on reset. 5 stacks for subroutine nesting. 8-bit real time clock/counter (TCC) with overflow interrupt. Two machine clocks or four machine clocks per instruction cycle. Power down mode. Programmable wake up from sleep circuit on I/O ports. Programmable free running on-chip watchdog timer.
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
*1
EM78P451S
8-Bit Microcontroller with OTP ROM 12 wake-up pins. 2 open-drain pins. 2 R-option pins. 32 programmable pull-high input pins. Packages:
* * * * * * *
40 pin DIP 600mil : EM78P451SP . 40 pin SOP 450mil: EM78P451SWM 44 pin QFP : EM78P451SAQ.
Four types of interrupts. External interrupt (/INT). SPI transmission completed interrupt. TCC overflow interrupt. Timer1 comparator match interrupt.
3
PIN ASSIGNMENT
Vss /INT DATA CLK P90 P91 P92/SDI P93/SDO P94/SCK P95//SS P50 P51 P52 P53 P54 P55 P56 P57 P80 P81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 EM78P451SP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 OSCO R-OSCI VDD
P71 P72 P67 P66 P65 P64 P63 P62 P61 P60 24 P87 23 22 21 20 19 18 P86 P85 P84 P83 P82 NC P81 P80 P57 P56 P55 17 16 15 14 13 12 1 P90 2 P91 3 P92/SDI 4 P93/SDO 5 P94/SCK 6 P95//SS 7 P50 8 P51 9 P52 10 P53 11 P54
P70//RESET P71 P72 P67 P66 P65 P64 P63
R-OSCI 39 40 41 42 43 44 P70//RESET NC NC NC VDD
33 34 35 36 37 38
32
31
30
29
28
27
26
25
P62 P61 P60 P87 P86 P85 P84 P83 P82
OSCO Vss /INT DATA CLK
EM78P451AQ
Fig. 1 Pin Assignment
2*
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM Table 1 Pin description
Symbol R-OSCI OSCO P90~P95 P80~P87 P70~P72 Pin No.
39 40 5~10 19~26 37~35
Type
I O I/O I/O I/O
Function Description In XTAL mode: Crystal input; In internal C, external R mode: 56Kohm5% pull high for 1.8432MHz. In XTAL mode: Crystal output; In RC mode: Instruction clock output. General bi-directional I/O port. All of its pins can be pulled-high by software. P90 and P91 are pin-change wake up pins. General bi-directional I/O port. All of its pins can be pulled-high by software. P80 and P81 are also used as the R-option pins. LED direct-driving pin with internal serial resistor used as output and is software defined. LED direct-driving pin with internal serial resistor used as output and is software defined. Code option bit 3 (REN): reset enable REN=0 => for reset pin REN=1 => for general purpose I/O (P70) Internal pull high resistor 220Kohm By connecting P74 and P76 together. P74 can be pulled-high by software and it is also a pin-change wake up pin. P76 can be defined as an open-drain output. By connecting P75 and P77 together. P75 can be pulled-high by software and it is also a pin-change wake up pin. P77 can be defined as an open-drain output. General bi-directional port. All of its pins can be pulled-high by software, and pin-change wake up pins. General bi-directional I/O port. All of its pins can be pulled-high individually by software. Power supply pin. Ground pin. An interrupt schmitt-triggered pin. The function of interrupt triggers at the falling edge. Users can enable it by software. Serial data in for SPI Serial data out for SPI. Serial clock for SPI. /Slave select for SPI.
P70/ RESET
37
I/O
CLK
4
I/O
DATA P60~P67 P50~P57 VDD VSS /INT SDI SDO SCK /SS
3
I/O
27~34 11~18 38 1
I/O I/O -
2
I
7 8 9 10
I/O I/O I/O I/O
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
*3
EM78P451S
8-Bit Microcontroller with OTP ROM
4
FUNCTION DESCRIPTION
WDT Timer
WDT Time-out
PC
STACK 1 STACK 2 STACK 3
Prescaler
Oscillator/ Timming Control
/ INT
ROM
STACK 4 STACK 5
R1(TCC)
Interrupt Control
Instruction Register
ALU RAM
Instruction Decoder R3 R4 ACC TMR1
Sleep & Wake Up Control
DATA & CONTROL BUS
IOC5 R5
IOC6 R6
IOC7 R7
IOC8 R8
IOC9 R9
SPI ENGIN
PPPPPPPP 55555555 01234567
PPPPPPPP 66666666 01234567
P 7 0
P 7 1
P 7 2
PPPPPPPP 88888888 01234567
P PPP 9 999 0 123 // SS DD IO
P 9 4 / S C K
P 5 5 / / S S
Fig. 2 Functional Block Diagram
4.1 Operational Registers
4.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4).
4.1.2 R1 (TCC)
Increased by the instruction cycle clock. Written and read by program as any other register.
4.1.3 R2 (Program Counter) & Stack
R2 and the hardware stacks are 12 bits wide. The structure is depicted in Fig. 3. Generates 4K x 13 on-chip ROM addresses to the relative programming instruction codes. One program page is 1024 words long. All the R2 bits are set to "1"s as a RESET condition occurs.
4*
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows jump to any location on one page. "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page "RET" ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2, A" allows the loading of an address from the "A" register to the lower 8 bits of PC, and the ninth and tenth bits (A8~A9) of PC are cleared. "ADD R2, A" allows a relative address be added to the current PC, and the ninth and tenth bits of PC are cleared. Any instruction that is written to R2 (e.g. "ADD R2, A", "MOV R2, A", "BC R2,6",) (except "TBL") will cause the ninth and tenth bits (A8~A9) of PC to be cleared. Thus, the computed jump is limited to the first 256 locations of any program page. "TBL" allows a relative address be added to the current PC (R2+AR2), and contents of the ninth and tenth bits (A8~A9) of PC are not changed. Thus, the computed jump can be on the second (or third, 4th) 256 locations on one program page. In case of EM78P451S, the most significant bits (A10~A11) will be loaded with the contents of bits PS0~PS1 in the status register (R3) upon the execution of a "JMP", "CALL", or any other instructions which writes to R2. All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would change the contents R2. Such instruction will need one more instruction cycle.
R3
A11 A10 A9 A8
A7 CALL RET RETL RETI
~
A0
Hardware Vector Software Vector User Memory Space
00 PAGE0 0000~03FF 01 PAGE1 0400~07FF 10 PAGE2 0800~0BFF 11 PAGE3 0C00~0FFF
Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5
On-chip Program Memory
Reset Vector
Fig. 3 Program Counter Organization
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
*5
EM78P451S
8-Bit Microcontroller with OTP ROM
4.1.4 R3 (Status Register)
7 GP 6 PS1 5 PS0 4 T 3 P 2 Z 1 DC 0 C
Bit7 (GP) General read/write bit. Bit6 (PS1) ~ 5 (PS0) Page select bits. PS0~PS1 are used to pre-select a program memory page. When executing a "JMP", "CALL", or other instructions which causes the program counter to be changed (e.g. MOV R2, A), PS0~PS1 are loaded into the 11th and 12th bits of the program counter where it selects selecting one of the available program memory pages. Note that RET (RETL, RETI) instruction does not change the PS0~PS1 bits. That is, the return will always be to the page from where the subroutine was called, regardless of the current setting of PS0~PS1 bits. PS1 bit is not used (read as "0") and cannot be modified in EM78P451S.
PS1 0 0 1 1 PS0 0 1 0 1 Program memory page [Address] Page 0 [000-3FF] Page 1 [400-7FF] Page 2 [800-BFF] Page 3 [C00-FFF]
Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and the "WDTC" commands, or during power up and reset to 0 with WDT timeout. Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. Bit 1 (DC) Auxiliary carry flag Bit 0 (C) Carry flag
4.1.5 R4 (RAM Select Register)
Bits 7~6 determine which bank is activated among the 4 banks. Bits 5~0 are used to select the registers (address: 00~3F) in the indirect addressing mode. If no indirect addressing is used, the RSR is used as an 8-bit general-purposed read/writer register. See the configuration of the data memory in Fig. 4.
6*
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
4.1.6 R5~R8 (Port 5 ~ Port8)
Four general 8 bits I/O registers Both P74 and P76 read or write data from the DATA pin, while both P75 and P77 read or write data from the CLK pin.
4.1.7 R9 (Port9)
A general 6-bit I/O register. The values of the two most significant bits are read as "0".
Aaddress R PAGE registers IOC PAGE registers
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF
(Indirect Addressing Register) (Time Clock Counter) (Program Counter) (Status Register) (RAM Select Register) (Port5) (Port6) (Port7) (Port8) (Port9) (SPI read buffer) (SPI write buffer) (SPI status buffer) (SPI control buffer) (Timer1 register) (Pulse width preset register) IOCC IOC5 IOC6 IOC7 IOC8 IOC9
Reserve CONT (Control Register) Reserve Reserve Reserve (I/O Port Control Register) (I/O Port Control Register) (I/O Port Control Register) (I/O Port Control Register) (I/O Port Control Register) Reserve Reserve (Timer1 Control Register)
IOCD (Pull_high Control Register) IOCE IOCF (WDT Control Register) (Interrupt Mask Register)
General Registers 1F 20 Bank0 3E Bank1 Bank2 Bank3
3F
R3F
(Interrupt Status Register)
Fig. 4 Data memory configuration
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
*7
EM78P451S
8-Bit Microcontroller with OTP ROM
4.1.8 RA (SPIRB: SPI Read Buffer)
Address
0X0A
Name
SPIRB/RA
Bit 7
SRB7
Bit 6
SRB6
Bit 5
SRB5
Bit 4
SRB4
Bit 3
SRB3
Bit 2
SRB2
Bit 1
SRB1
SRB7~SRB0 are the 8-bit data when complete transmission by SPI.
4.1.9 RB (SPIWB: SPI Write Buffer)
Address 0x0B
Name
Bit 7
Bit 6
SWB6
Bit 5
SWB5
Bit 4
SWB4
Bit 3
SWB3
Bit 2
SWB2
Bit 1
SWB1
Bit 0
SWB0
SPIWB/RB SWB7
SWB7~SWB0 are the 8-bit data that are waiting for transmission by SPI.
4.1.10 RC (SPIS: SPI Status Segister)
Address
0x0C
Name
SPIS/RC
Bit 7
--
Bit 6
--
Bit 5
--
Bit 4
TM1IF
Bit 3
OD3
Bit 2
OD4
Bit 1
RBFIF
Bit 0
RBF
Bits 7 ~ 5 Bit 4 (TM1IF):
Not used.
0 = In timer1 mode, receiving not completed yet, and an interrupt does not occur. 1 = In timer1 mode, receiving completed, and an interrupt occurs if enabled. Bit 3 (OD3): Open-Drain Control bit 0 = Open-drain disable for SDO. 1 = Open-drain enable for SDO, Bit 2 (OD4): Open-Drain Control bit 0 = Open-drain disable for SCK. 1 = Open-drain enable for SCK, Bit 1 (RBFIF):Read Buffer Full Interrupt Flag 0 = Receiving not completed yet; and SPIRB has not fully exchanged. 1 = Receiving completed, SPIRB is fully exchanged, and an interrupt occurs if enabled. Bit 0 (0RBF):Read Buffer Full flag 0 = Receiving not completed yet, and SPIRB has not fully exchanged. 1 = Receiving completed; SPIRB is fully exchanged.
8*
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
4.1.11 RD (SPIC: SPI Control Register)
Address
0x0D
Name
SPIC/RD
Bit 7
CES
Bit 6
SPIE
Bit 5
SRO
Bit 4
SSE
Bit 3
-
Bit 2
SBRS2
Bit 1
SBRS1
Bit 0
SBRS0
Bit 7 (CES): Clock Edge Select bit 0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on hold during the low level. 1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on hold during the high level. Bit 6 (SPIE): SPI Enable bit 0= Disable SPI mode 1= Enable SPI mode Bit 5 (SRO): SPI Read Overflow bit 0 = No overflow 1 = A new data is received while the previous data is still being held in the SPIB register. In this situation, the data in SPIS register will be destroyed. To avoid setting this bit, users had better read SPIRB register even if only the transmission is implemented.
NOTE This can only occur in slave mode.
Bit 4 (SSE): SPI Shift Enable bit 0 = Reset as soon as the shifting is complete, and the next byte is ready to shift. 1 = Start to shift, and keep on 1 while the current byte is still being transmitted.
NOTE This bit will reset to 0 at every one-byte transmission by the hardware
Bit 2~Bit 0 (SBRS): SPI Baud Rate Select bits SPI baud rate table is illustrated in SPI section in later pages.
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
*9
EM78P451S
8-Bit Microcontroller with OTP ROM
4.1.12 RE (TMR1: Timer1 register)
Address
0X0E
Name
TMR1/RE
Bit 7
TMR17
Bit 6
TMR16
Bit 5
TMR15
Bit 4
TMR14
Bit 3
TMR13
Bit 2
TMR12
Bit 1
Bit 0
TMR11 TMR10
TMR17~TMR10 is bit set of timer1 register and it increases until the value matches PWP and then, it resets to 0.
4.1.13 RF (PWP: Pulse width preset register)
Address Name
0x0F PWP/RF
Bit 7
PWP7
Bit 6
PWP6
Bit 5
PWP5
Bit 4
PWP4
Bit 3
PWP3
Bit 2
PWP2
Bit 1
PWP1
Bit 0
PWP0
PWP7~PWP0 is bit set of pulse width preset in advance for the desired width of baud clock.
4.1.14 R20~R3E (General Purpose Register)
RA~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.
4.1.15 R3F (Interrupt Status Register)
Address Name
0x3F ISR/R3F
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
TM1IF
Bit 2
SPIIF
Bit 1
EXIF
Bit 0
TCIF
Bits 7~4
are not used and read as "0".
Bit 3 (TM1IF) Timer1 interrupt flag. Set by the comparator at Timer1 application, flag cleared by software. Bit 2 (SPIIF) SPI interrupt flag. Set by data transmission complete, flag cleared by software. Bit 1 (EXIF) External interrupt flag. Set by falling edge on /INT pin, flag cleared by software Bit 0 (TCIF) the flag of the TCC overflow interrupt. Set as TCC overflow; flag cleared by software. "1" means interrupt request, "0" means non-interrupt. R3F can be cleared by instruction, but cannot be set by instruction. IOCF is the interrupt mask register. Note that to read R3F will result to "logic AND" of R3F and IOCF.
4.2 Special Purpose Registers
4.2.1 A (Accumulator)
Internal data transfer, or instruction operand holding. A non-addressable register.
10 * Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
4.2.2
7
/PHEN
CONT (Control Register)
6
/INT
5
-
4
-
3
PAB
2
PSR2
1
PSR1
0
PSR0
Bit 7 (/PHEN) I/O pin pull-high enable flag. 0: For P60~P67, P74~P75 and P90~P95, the pull-high function is enabled. 1: The pull-high function is disabled. Bit 6 (INT) An interrupt enable flag cannot be written by the CONTW instruction. 0: interrupt masked by the DISI instruction. 1: interrupt enabled by the ENI or RETI instruction. Bit5, 4 Not used, and to be read as "0".
Bit 3 (PAB) Prescaler assignment bit. 0: TCC 1: WDT Bit 2 (PSR2) ~ Bit 0 (PSR0) TCC/WDT prescaler bits.
PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
Bits 0~3, and 7 of the CONT register are readable and writable.
4.2.3
IOC5 ~ IOC9 (I/O Port Control Register)
"1" put the relative I/O pin into high impedance, while "0" put the relative I/O pin as output. Both P74 and P76 should not be defined as output pins at the same time. This also applies to both P75 and P77. Only the lower 6 bits of the IOC9 register are used.
4.2.4
Address
0x0C
IOCC (T1CON: Timer1 control register)
Name
T1CON/IOCC
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
TM1E
Bit 1
TM1P1
Bit 0
TM1P0
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
* 11
EM78P451S
8-Bit Microcontroller with OTP ROM Bit2 (TM1E): Timer1 Function Enable bit 0 = Disable timer1 function as default. 1 = Enable timer1 function. Bit1~Bit0 (TM1P): Timer1 Prescaler bit Timer1 prescaler table for FOSC will be illustrated in the Section on Timer1 in later pages.
4.2.5
7
S7
IOCD (Pull-high Control Register)
6
-
5
-
4
-
3
/PU9
2
/PU8
1
/PU6
0
/PU5
The default values of /PU5, /PU6, /PU8, and /PU9 are one, which means the pull-high function is disabled. /PU6 and /PU9 are "AND" gating with /PHEN, that is, when each one is written as "0" pull high is enabled. S7 defines the driving ability of the P70-P72. 0: Normal output. 1: Enhance the driving ability of LED.
4.2.6
7
-
IOCE (WDT Control Register)
6
ODE
5
WDTE
4
SLPC
3
ROC
2
-
1
-
0
/WUE
Bits 7, and1~2 Not used. Bit 6 (ODE) Open-drain control bit. 0: Both P76 and P77 are normally I/O pins. 1: Both P76 and P77 pins have the open-drain function inside. The ODE bit can be read and written. Bit 5 (WDTE) Control bit used to enable Watchdog timer. The WDTE bit can be used only if ENWDT, the CODE Option bit, is "1". If the ENWDT bit is "1", then WDT can be disabled/enabled by the WDTE bit. 0: Disable WDT. 1: Enable WDT. The WDTE bit is not used if ENWDT, the CODE Option bit ENWDT, is "0". That is, if the ENWDT bit is "0", WDT is always disabled no matter what the WDTE bit is. The WDTE bit can be read and written.
12 * Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM Bit 4 (SLPC) This bit is set by hardware at the falling edge of wake-up signal and is cleared in software. SLPC is used to control the oscillator operation. The oscillator is disabled (oscillator is stopped, and the controller enters the SLEEP2 mode) on the high-to-low transition and is enabled (the controller is awakened from SLEEP2 mode) on low-to-high transition. In order to ensure the stable output of the oscillator, once the oscillator is enabled again, there is a delay for approximately 18 ms (oscillator start-up timer (OST)) before the next program instruction is executed. The OST is always activated by wake-up from sleep mode whether the Code Option bit ENWDT is "0" or not. After waking up, the WDT is enabled if Code Option ENWDT is "1". The block diagram of SLEEP2 mode and wake-up caused by input triggered is depicted in Fig. 5. The SLPC bit can be read and written. Bit 3 (ROC) ROC is used for the R-option. Setting ROC to "1" will enable the status of R-option pins (P80, P81) to be read by the controller. Clearing ROC will disable the R-option function. Otherwise, the R-option function is introduced. Users must connect the P81 pin or/and P80 pin to VSS by a 560K external resistor (Rex). If Rex is connected/disconnected with VDD, the status of P80 (P81) will be read as "0"/"1" (refer to Fig. 7(b)). The ROC bit can be read and written. Bit 0 (/WUE) Control bit used to enable the wake-up function of P60~P67, P74~P75, and P90~P91. 0: Enable the wake-up function. 1: Disable the wake-up function. The /WUE bit can be read and written.
4.2.7
7
-
IOCF (Interrupt Mask Register)
6
-
5
-
4
-
3
TM1IE
2
SPIIE
1
EXIE
0
TCIE
Bits 4~7 Not used. Individual interrupt is enabled by setting its associated control bit in IOCF to "1". The IOCF Register could be read and written. Bit 3 (TM1IE) TM1IE interrupt enable bit. 0: disable TM1IE interrupt 1: enable TM1IE interrupt Bit 2 (SPIIE) SPI interrupt enable bit. 0: disable SPI interrupt 1: enable SPI interrupt
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
* 13
EM78P451S
8-Bit Microcontroller with OTP ROM Bit 1 (EXIE) EXIF interrupt enable bit. 0: disable EXIF interrupt 1: enable EXIF interrupt Bit 0 (TCIE) TCIF interrupt enable bit. 0: disable TCIF interrupt 1: enable TCIF interrupt
/W U E
O scillator
E n ab le D isab le R eset
PD R C LK C L
/W U E
Q Q
VCC
C lear
S et
8
/W U E
fro m S /W
P 60~P 67
VCC
/W U E /P H E N 4
P 74~P 75, P 90~P 91
Fig. 5 Block Diagram of Sleep Mode and Wake-up Circuits on I/O Ports
4.3 TCC/WDT Presacler
An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is available for either the TCC or WDT only at any given time, and the PAB bit of CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits determine the prescale ratio. The prescaler is cleared each time the instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to WDT mode, are cleared by the WDTC or SLEP instructions. Fig. 6 depicts the circuit diagram of TCC/WDT. R1(TCC) is an 8-bit timer/counter. TCC will increase by one at every instruction cycle (without prescaler).
14 * Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM The watchdog timer is a free running on-chip RC oscillator. The WDT will keep running even when the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during the normal mode by software programming (if Code Option bit ENWDT is "1"). Refer to WDTEbit of IOCE register. Without presacler, the WDT time-out period is approximately 18 ms1.
4.4 I/O Ports
The I/O registers, from Port 5 to Port 9, are bi-directional tri-state I/O ports. P60~P67, P74~P75, and P90~P91 provide internal pull-high. P60~P67, P74~P75, and P90~P95 provide programmable wake-up function through software. P76~P77 can have open-drain output by software control. P80~P81 are the R-option pins which are enabled by software. When the R-option function is used, it is recommended that P80 and P81 are used as output pins. During R-option enabled state, P80 and P81 must be programmed as input pins. If an external resistor is connected to P80 (P81) for the R-option function, the current consumption should be taken as an important factor in the applications for low power consideration. The I/O ports can be defined as "input" or "output" pins by the I/O control registers (IOC5~IOC9) under program control. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig. 7. Note that the reading path source of input and output pins is different when reading the I/O port.
CLK(=Fosc/2)
Data Bus
1
M U X
0
SYNC 2 cycles
TCC(R1)
PAB
0
TCC overflow interrupt
WDT
1
M U X
8-bit Counter PSR0~PSR2 8 - to -1 MUX
0 1
WDTE (in IOCE)
MUX
PAB
WDT timeout
Fig. 6 Block Diagram of TCC WDT
1
NOTE: Vdd = 5V, set up time period = 16.2ms 30% Vdd = 3V, set up time period = 18.0ms 30%
* 15
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
PCRD
Q
PD R CLK QC L
PCWR
PORT
Q
P RD C CLK QL
IOD PDWR
0 1
M U X
PDRD
Fig. 7 (a) The Circuit of I/O Port and I/O Control Register
PCRD VCC ROC
Q P D R CLK C L
Weakly Pull-up
PCWR
Q
PORT
Q Q
P R
IOD
D
C CLK L
PDWR
0 Rex* 1
M U X
PDRD
*The Rex is 560K ohm external resistor
Fig.7(b) The Circuit of I/O Port with R-option (P80, P81)
16 *
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
4.5 SERIAL PERIPHERAL INTERFACE MODE
4.5.1 Overview & Features
Overview: Figures 8, 9, and 10 show how EM78P451S communicates with other devices through SPI module. If EM78P451S is a master controller, it sends clock through the SCK pin. A couple of 8-bit data are transmitted and received at the same time. However, if EM78P451S is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted based on both the clock rate and the selected edge. Features: Operation in either Master mode or Slave mode, Three-wire or four-wire synchronous communication; that is, full duplex Programmable baud rates of communication, Programming clock polarity, (RD bit7) Interrupt flag available for the read buffer full, Up to 8 MHz ( maximum ) bit frequency,
SDO SPIR Reg SPIW SPIW Reg Reg /SS SPIS Reg Bit 7 Master Device SCK Slave Device SDI SPI Module
Fig. 8 SPI Master/Slave Communication
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
* 17
EM78P451S
8-Bit Microcontroller with OTP ROM
SDI SDO SCK /SS
Vdd Master
P50 P51 P52 P53
SDO SDI SCK /SS
SDO SDI SCK /SS
Slave Device 1
Slave 2 for master 1
SDO SDI SCK /SS
SDO SDI SCK /SS
Slave Device 2
Slave Device 3
Slave Device 4
Fig. 9 The SPI Configuration of Single-Master and Multi-Slave
SDI SDO SCK /SS
SDI SDO SCK /SS
Master1 or P50 Slave1 P51
P52 P53
Master2 or P50 P51 Slave6
P52 P53
SDO SDI SCK /SS
SDO SDI SCK /SS
SDO SDI SCK /SS
SDO SDI SCK /SS
Slave 3 for Master 1/2 Slave 4 for Master1/2
Slave 5 for Master 2
Fig. 10 The SPI Configuration of Single-Master and Multi-Slave
18 *
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
4.5.2 SPI Function Description
Read W rite
RBF S e t to 1
RBFI
S P IR
re g
SE
S P IW
re g
B u ffe r F u ll D e te c to r
S P IS
P 9 2 /S D I
b it 0
re g
s h ift rig h t
b it 7
S P IC re g P 9 3 /S D O
Edge S e le c t
SB R 0 ~SB R2
P 9 5 / /S S
/ SS
T sco
SBR 2~SB R 0 8
C lo c k S e le c t 2
N o is e F ilte r
P re sc aler 4 , 8 , 1 6, 32 , 6 4
Edge S e le c t
T M R 1 /2 S P IC b it6
P 9 4 /S C K
Fig. 11 SPI Block Diagram
SPI
SPI Write Register (0X0B)
/SS
SPI Read Register (0X0A)
SDO
SDI Shift Clock
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
SPI Mode Select Register
210 SPIC
The following describes the function of each block and explains how to carry out the SPI communication with the signals depicted in Fig.11 and Fig.12:
8-1 MUX
SPI Shift Buffer
FOSC
7~0 SPIWB
10 764 10 T1CON SPIC SPIS DATA BUS
2 INTC
4 SPIC
7~0 SPIRB
Fig. 12 The Function Block Diagram of SPI Transmission
* 19
EM78P451S
8-Bit Microcontroller with OTP ROM P92/SDI:Serial Data In. P93/SDO:Serial Data Out. P94/SCK: Serial Clock. P95//SS:/Slave Select (Option). This pin (/SS) may be required during a slave mode. RBF: Set by Buffer Full Detector, and reset in software. RBIF: Set by Buffer Full Detector, and reset in software. Buffer Full Detector: Sets to 1 when an 8-bit shifting is completed. SSE: Loads the data in SPIS register, and begin to shift SPIS reg.:Shifting byte in and out. The MSB is shifted first. Both the SPIS register and the SPIW register are loaded at the same time. Once data are written, SPIS starts transmission / reception. The received data will be moved to the SPIR register as the shifting of the 8-bit data is completed. The RBF (Read Buffer Full) flag and the RBFI(Read Buffer Full Interrupt) flag are then set. SPIR reg.: Read buffer. The buffer will be updated as the 8-bit shifting is completed. The data must be read before the next reception is completed. The RBF flag is cleared as the SPIR register reads. SPIW reg.:Write buffer. The buffer will deny any attempt to write until the 8-bit shifting is completed. The SSE bit will be kept in 1 if the communication is still undergoing. This flag must be cleared as the shifting is completed. Users can determine if the next write attempt is available. SBRS2~SBRS0:Programming the clock frequency/rates and sources. Clock Select:Selecting either the internal or external clock as the shifting clock. Edge Select:Selecting the appropriate clock edges by programming the CES bit
4.5.3 SPI Signal & Pin Description
The detailed functions of the four pins, SDI, SDO, SCK, and /SS, which are shown in Fig. 9, are as follows: SDI/P92 (Pin 7): Serial Data In, Receive serially, the Most Significant Bit (MSB) first, Least Significant Bit (LSB) last, Defined as high-impedance, if not selected, Program the same clock rate and clock edge to latch on both the master and slave devices,
20 * Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM The received byte will update the transmitted byte, Both the RBF and RBFIF bits (located in Register 0x0C) will be set as the SPI operation is completed. Timing is shown in Fig.13 and14. SDO/P93 (Pin 8): Serial Data Out, Transmit serially; the Most Significant Bit (MSB) first, Least Significant Bit (LSB) last, Program the same clock rate and clock edge to latch on both the master and slave devices, The received byte will update the transmitted byte, The CES (located in Register 0x0D) bit will be reset, as the SPI operation is completed. Timing is shown in Fig.13 and 14. SCK/P94 (Pin 9): Serial Clock Generated by a master device Synchronize the data communication on both the SDI and SDO pins The CES (located in Register 0x0D) is used to select the edge to communicate. The SBR0~SBR2 (located in Register 0x0D) is used to determine the baud rate of communication The CES, SBR0, SBR1, and SBR2 bits have no effect in the slave mode Timing is show in Fig.13 and 14 /SS/P95 (Pin 10): Slave Select; negative logic, Generated by a master device to signify the slave(s) to receive data, Goes low before the first cycle of SCK appears, and remains low until the last (eighth) cycle is completed, Ignores the data on the SDI and SDO pins while /SS is high, because the SDO is no longer driven. Timing is shown in Fig.13 and Fig. 14.
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
* 21
EM78P451S
8-Bit Microcontroller with OTP ROM
4.5.4 Programmed the related registers
As the SPI mode is defined, the related registers of this operation are shown in Table 2 and Table 3. Table 2 Related Control Registers of the SPI Mode
Address 0x0D 0x0F Name Bit 7 Bit 6 SPIE -Bit 5 SRO -Bit 4 SSE -Bit 3 -TM1IE Bit 2 SBR2 SPIIE Bit 1 SBR1 EXIE Bit 0 SBR0 TCIE
*SPIC/RD CES INTC/IOCF --
SPIC: SPI Control Register. Bit 7 (CES): Clock Edge Select bit 0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on hold during the low level. 1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on hold during the high level. Bit 6 (SPIE):SPI Enable bit 0 = Disable SPI mode 1 = Enable SPI mode Bit 5 (SRO):SPI Read Overflow bit 0 = No overflow. 1 = A new data is received while the previous data is still being on hold in the SPIB register. Under this condition, the data in SPIS register will be destroyed. To avoid setting this bit, users should read the SPIRB register even if the transmission is implemented only.
NOTE This can only occur under slave mode.
Bit 4 (SSE):SPI Shift Enable bit 0 = Reset as soon as the shifting is completed and the next byte is ready to shift. 1 = Start to shift, and stays on 1 while the current byte continues to transmit.
NOTE This bit can be reset by hardware only.
22 *
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM Bit 2~0 (S BRS): SPI Baud Rate Select Bits
SBRS2 (Bit 2) 0 0 0 0 1 1 1 1 SBRS1 (Bit 1) 0 0 1 1 0 0 1 1 SBRS0 (Bit 0) 0 1 0 1 0 1 0 1 Mode Master Master Master Master Master Slave Slave Master Baud Rate Fsco/2 Fsco/4 Fsco/8 Fsco/16 Fsco/32 /SS enable /SS disable TMR1/2
NOTE In master mode, /SS is disable.
INTC: Interrupt control register Bit 3 (TM1IE) TM1IE interrupt enable bit. 0: disable TM1IE interrupt 1: enable TM1IE interrupt Bit 2 (SPIIE) SPI interrupt enable bit. 0: disable SPI interrupt 1: enable SPI interrupt Bit 1 (EXIE) EXIF interrupt enable bit. 0: disable EXIF interrupt 1: enable EXIF interrupt Bit 0 (TCIE) TCIF interrupt enable bit. 0: disable TCIF interrupt 1: enable TCIF interrupt Table 3 Related Status/Data Registers of the SPI Mode
Address
0X0A 0x0B 0x0C
Name
SPIRB/RA SPIWB/RB SPIS/RC
Bit 7
SRB7 SWB7 0
Bit 6
SRB6 SWB6 0
Bit 5
SRB5 SWB5 0
Bit 4
SRB4 SWB4 TM1IF
Bit 3
SRB3 SWB3 OD3
Bit 2
SRB2 SWB2 OD4
Bit 1
SRB1 SWB1 RBFIF
Bit 0
SRB0 SWB0 RBF
SPIRB: SPI Read Buffer. Once the serial data is received completely, it will load to SPIRB from SPISR. The RBF bit and the RBFIF bit in the SPIS register will be set also. SPIWB: SPI Write Buffer. As a transmitted data is loaded, the SPIS register stands by and start to shift the data when sensing SCK edge with SSE set to "1".
* 23
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM SPIS: SPI Status register Bit 4 (TM1IF):Timer1 interrupt flag. Bit 3 (OD3)Open-Drain Control bit (P93) 0 = Open-drain disable for SDO. 1 = Open-drain enable for SDO, Bit 2 (OD4):Open Drain-Control bit (P94) 0 = Open-drain disable for SCK. 1 = Open-drain enable for SCK Bit 1 (RBFIF):Read Buffer Full Interrupt flag 1 = Receive is completed, SPIB is full, and an interrupt occurs if enabled. 0 = Receive is ongoing, SPIB is empty. Bit 0 (RBF):Read Buffer Full flag 0 = Receive is ongoingt, SPIB is empty. 1 = Receive is completed, SPIB is full.
4.5.5 SPI Mode Timing
The edge of SCK is selected by programming bit CES. The waveform shown in Fig.13 is applicable regardless of whether the EM78P451S is under master or slave mode with /SS disabled. However, The waveform in Fig. 14 can only be implemented in slave mode with /SS enabled.
Fig. 13 SPI Mode with /SS Disable
24 *
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
Fig. 14 SPI Mode with /SS Enable
4.5.6 Software Application of SPI
Example for SPI: For Master ORG 0X0 SETTING: CLRA IOW 0X05 IOW 0X06 MOV 0X05,A MOV A,@0B11001111 CONTW MOV A,@0B00010001 IOW 0X0E MOV A,@0B00000000 IOW 0X0F MOV A,@0x07 IOW 0x09 MOV A,@0B10000000
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
;Set Port5 output ;Set Port6 output
;Set prescaler for WDT
;Disable wakeup function
;Disable interrupt
;SDI input and SDO, SCK output
;Clear RBF and RBFIF flag
* 25
EM78P451S
8-Bit Microcontroller with OTP ROM MOV 0x0C,A MOV A,@0B11100000 MOV 0X0D,A START: WDTC BC 0X0C,1 MOV A,@0XFF MOV 0X05,A MOV 0X0A,A MOV A,@0XAA MOV 0X0B,A BS 0X0D,4 NOP JBC 0X0D,4 JMP $-2 BC 0X03,2 CALL DELAY MOV A,0X0A XOR A,@0X5A JBS 0X03,2 JMP START FLAG: MOV A,@0X55 MOV 0X05,A CALL DELAY JMP START DELAY: ; (user's program) EOP ORG 0XFFF JMP SETTING
26 * Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
;Select clock edge and enable SPI
;Clear RBFIF flag
;Show a signal at Port5 ;Move FF at read buffer ;Move AA at write buffer
;Start to shift SPI data
;Polling loop for checking SPI transmission completed
;To catch the data from slaver
;Compare the data from slaver
;Show the signal when receiving correct data from slaver
EM78P451S
8-Bit Microcontroller with OTP ROM For Slaver ORG 0X0 INITI: JMP INIT ORG 0X2 INTERRUPT: MOV A,@0X55 MOV 0X06,A MOV A,@0B11100110 MOV 0X0D,A BS 0X0D,4 MOV A,@0X00 as 00 MOV 0X0B,A BS 0X0D,4 NOP JBC 0X0D,4 JMP $-2 BS 0X0D,4 BC 0X03,2 MOV A,0X0A MOV 0X06,A XOR A,@0XAA JBS 0X03,2 JMP $-6 JMP SPI ;Read master's data from read buffer ;Check pass signal from read buffer ;Keep SSE at 1 to wait for SCK signal in order to shift data ;Polling loop for checking SPI transmission completed ;Keep SSE at 1 to wait for SCK signal in order to shift data ;Keep SSE at 1 to wait for SCK signal in order to shift data ;Move 00 to write buffer in order to keep master's read buffer ;Show a signal at Port 6 when entering interrupt ;Enable SPI, /SS disabled ;Interrupt address
ORG 0X30 INIT: CLRA IOW 0X05 IOW 0X06
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
* 27
EM78P451S
8-Bit Microcontroller with OTP ROM MOV 0x05,A MOV 0X06,A MOV A,@0XFF IOW 0X08 MOV A,@0B11001111 CONTW MOV A,@0B00010001 IOW 0X0E MOV A,@0B00000010 IOW 0XF ENI MOV A,@0B00110111 IOW 0x09 BC 0X3F,1 NOP JBS 0X3F,1 JMP $-2 JMP INTERRUPT SPI: BS 0X0D,4 WDTC MOV A,@0X0F MOV 0X06,A JBC 0X08,1 JMP SPI MOV A,@0X5A MOV 0X0B,A NOP JBC 0X0D,4 JMP $-2 BS 0XD,4
28 * Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
;Set prescaler for WDT
;Disable wakeup function
;Enable external interrupt
;Clear RBFIF flag
;Polling loop for checking interrupt occurence
;Keep SSE enabled as long as possible
;Show a signal when entering SPI loop
;Choose P81 as a signal button
;Move 5A into write buffer when P81 button is pushed
;Polling loop for checking SPI transmission completed
EM78P451S
8-Bit Microcontroller with OTP ROM NOP NOP MOV A,@0XF0 MOV 0X06,A MOV A,@0X00 MOV 0X0B,A NOP JBC 0X0D,4 JMP $-2 BS 0X0D,4 BS 0x0C,7 BC 0x0C,1 NOP JMP SPI DELAY: ; (user's program) ;Send a signal to master to prevent infinite loop ;Display at Port6 when P81 button is pushed
EOP ORG 0XFFF JMP INITI
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
* 29
EM78P451S
8-Bit Microcontroller with OTP ROM
4.6 Timer 1
Clock output Sets TMR1IF OSC/4
4.6.1 Overview
Timer1(TMR1) is an eight-bit clock counter with a programmable prescaler. It is designed for the SPI module as a baud rate clock generator. TMR1 can be read and Comarator written and cleared on any reset conditions. If employed, it can be turned down for EQ Prescaler power saving by setting TMR1EN bit [T1CON<2>] to 0.1:16 1:1 to
increase
OSC/2
4.6.2 PWP FunctionTMR1 description
reset
Fig. 15 shows TIMER1 block diagram. Each signal and block is described as follows: Fig. 15 TIMER1 Block Diagram OSC/4:Input clock. Prescaler: Option of 1:1, 1:4, 1:8, and 1:16 defined by T1P1 and T1P02 (T1CON<1, 0>). It is cleared when a value is written to TMR1 or T1CON, and during any kind of reset as well. PWP: Pulse width preset register. The desired width of baud clock is written in advance. TMR1: Timer 1 register. TMR1 increases until it matches with PWP, and then resets to 0. If it is chosen optionally in the SPI mode, its output is fed as a shifting clock. Comparator: To change the output status while a match occurs. The TMR1IF flag will be set at the same time.
4.6.3 Programmed the related registers
The related registers of the defining TMR1 operation are shown in Table 4 and Table 5 Table 4 Related Control Registers of the TMR1
Address
0x0C 0x0F
Name
SPIS/RC INTC/IOCF
Bit 7
0 0
Bit 6
0 0
Bit 5
0 0
Bit 4
TM1IF 0
Bit 3
OD3 TM1IE
Bit 2
OD4 SPIIE
Bit 1
RBFIF EXIE
Bit 0
RBF TCIE
Table 5 Related Status/Data Registers ofTMR1
Address
0X0E 0x0F 0x0C
Name
TMR1/RE PWP/RF T1CON/IOCC
Bit 7
TMR17 PWP7 0
Bit 6
TMR16 PWP6 0
Bit 5
TMR15 PWP5 0
Bit 4
TMR14 PWP4 0
Bit 3
TMR13 PWP3 0
Bit 2
TMR12 PWP2 TM1E
Bit 1
TMR11 PWP1 TM1P1
Bit 0
TMR10 PWP0 TM1P0
30 *
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM TMR1: Timer1 Register TMR17~TMR10 is bit set of Timer1 register and it increases until the value matches PWP and then it reset to 0. PWP: Pulse Width Preset Register PWP7~PWP0 is bit set of pulse width preset for the desired width of baud clock in advance. T1CON: Timer1 Control Register Bit 2 (TM1E): Timer1 enable bit Bit 1 (TM1P1) and Bit 0 (TM1P): Timer1 prescaler for FSCO
TM1P1
0 0 1 1
TM1P0
0 1 0 1
Prescaler Rate
1:1 1:4 1:8 1:16
4.7 RESET and Wake-up
A RESET is initiated by (1) Power on reset, or (2) /RESET pin input "low", or (3) WDT timeout. (if enabled)
VDD
Oscillator
D Q CLK CLR
CLK
Poweron Reset Voltage Detector
WDTE
WDT timeout
WDT
Setup Time
Reset
Fig. 16 Block Diagram of Reset
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
* 31
EM78P451S
8-Bit Microcontroller with OTP ROM EM78P451S POR voltage range is 1.2V~2.0V. Under customer application, when power is OFF, Vdd must drop to below 1.2V and remains OFF for 10us before power can be switched ON again. This way, the EM78P451S will reset and work normally. The extra external reset circuit will work well if Vdd can rise at very fast speed (50 ms or less). However, under most cases where critical applications are involved, extra devices are required to assist in solving the power-up problem. The device is kept in a RESET condition for a period of approx. 18ms2 (one oscillator start-up timer period) after the reset is detected and Fig.16 is the block diagram of reset. Once the RESET occurs, the following functions are performed. The oscillator is running, or will be started. The Program Counter (R2) is set to all "1". When power is switched on, bits 5~6 of R3 and the upper 2 bits of R4 are cleared. All I/O port pins are configured as input mode (high-impedance state). The Watchdog timer and prescaler are cleared. The Watchdog timer is enabled if Code Option bit ENWDT is "1". The CONT register is set to all "1" except bit 6 (INT flag). Bits 3,6 of IOCE register are cleared, bits 0,4~5 of IOCE register are set to "1". Bits 0 of R3F and bits 0 of IOCF registers are cleared. The sleep mode (power down) is achieved by executing the SLEP instruction (named as SLEEP1 MODE). While entering sleep mode, the WDT (if enabled) is cleared but keeps on running. The controller is awakened by WDT timeout (if enabled), and it will cause the controller to reset. The T and P flags of R3 are used to determine the source of the reset (wake-up). In addition to the basic SLEEP1 MODE, EM78P451S has another sleep mode (caused by clearing "SLPC" bit of IOCE register, designated as SLEEP2 MODE). In the SLEEP2 MODE, the controller can be awakened by(a) Any one of the wake-up pins is set to "0." (refer to Fig.17). Upon waking, the controller will continue to execute the program in-line. In this case, before entering SLEEP2 MODE, the wake-up function of the trigger sources (P60~P67, P74~P75, and P90~P91)should be selected (e.g. input pin) and enabled (e.g. pull-high, wake-up control). One caution should be noted is that after waking up, the WDT is enabled if Code Option bit ENWDT is "1". The WDT operation (to be enabled or disabled) should be appropriately controlled by software after waking up. (b) WDT time-out (if enabled). or external reset input on /RESET pin will trigger a controller reset..
2
NOTE: Vdd = 5V, set up time period = 16.20ms 30% Vdd = 3V, set up time period = 18.0ms 30%
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
32 *
EM78P451S
8-Bit Microcontroller with OTP ROM Table 6 Usage of Sleep and Sleep2 Mode
Usage of Sleep and Sleep2 Mode
SLEEP2 SLEEP
(a) Before SLEEP 1. Set Port6 or P74 or P75 Input 2. Enable Pull-High and set WDT prescaler over 1:1 (Set CONT.7 and CONT.3 ~ CONT.0) 3. Enable Wake-up (Set IOCB or IOCE.0) 4. Execute Seep2 (Set IOCE.4) (b) After Wake-up 1. Next instruction 2. Disable Wake-up 3. Disable WDT (Set IOCE.5)
(a) Before SLEEP 1. Execute SLEP instruction
(b) After Wake-up 1. Reset
If Port6 Input Status Changed Wake-up is used to wake-up the EM78P451S (Case [a] above), the following instructions must be executed before entering SLEEP2 mode:
MOV IOW MOV CONTW MOV IOW After Wake-up NOP MOV IOW A, @11111111b IOC6 A, @0xxx1010b A, @xx00xxx0b IOCE ; Set Port6 input ; Set Port6 pull-high, WDT prescaler, prescaler must set over 1:1 ; Enable Port6 wake-up function, Enable SLEEP2
A, @ xx01xxx1b IOCE
; Disable Port6 wake-up function; Disable WDT
After waking up from the SLEEP2 mode, WDT is automatically enabled. The WDT enabled/disabled operation after waking up from SLEEP2 mode should be appropriately defined in the software. To avoid a reset from occurring when the Port 6 Input Status Changed Interrupt enters into interrupt vector or is used to wake-up the MCU, the WDT prescaler must be set above the 1:1 ratio. Table 7 The Summary of the Initialized Values for Registers
Address
N/A
Name
IOC5
Reset Type Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT
Bit 7
C57 1 1 P C67 1 1 P C77 1 1 P C87 1 1
Bit 6
C56 1 1 P C66 1 1 P C76 1 1 P C86 1 1
Bit 5
C55 1 1 P C65 1 1 P C75 1 1 P C85 1 1
Bit 4
C54 1 1 P C64 1 1 P C74 1 1 P C84 1 1
Bit 3
C53 1 1 P C63 1 1 P C73 1 1 P C83 1 1
Bit 2
C52 1 1 P C62 1 1 P C72 1 1 P C82 1 1
Bit 1
C51 1 1 P C61 1 1 P C71 1 1 P C81 1 1
Bit 0
C50 1 1 P C60 1 1 P C70 1 1 P C80 1 1
N/A
IOC6
N/A
IOC7
N/A
IOC8
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
* 33
EM78P451S
8-Bit Microcontroller with OTP ROM
Address
Name
Reset Type Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
Bit 7
P C97 1 1 P /PHE N 1 1 P U P P 0 0 P 1 1 **P GP 0 0 P RSR. 1 0 0 P P57 U P P P67 U P P P77 U P P P87 U P
Bit 6
P C96 1 1 P /INT 0 P P U P P 0 0 P 1 1 **P PS1 0 0 P RSR. 0 0 0 P P56 U P P P66 U P P P76 U P P P86 U P
Bit 5
P C95 1 1 P 1 1 P U P P 0 0 P 1 1 **P PS0 0 0 P U P P P55 U P P P65 U P P P75 U P P P85 U P
Bit 4
P C94 1 1 P 1 1 P U P P 0 0 P 1 1 **P T t t t U P P P54 U P P P64 U P P P74 U P P P84 U P
Bit 3
P C93 1 1 P PAB 1 1 P U P P 0 0 P 1 1 **P P t t t U P P P53 U P P P63 U P P P73 U P P P83 U P
Bit 2
P C92 1 1 P PSR 2 1 1 P U P P 0 0 P 1 1 **P Z U P P U P P P52 U P P P62 U P P P72 U P P P82 U P
Bit 1
P C91 1 1 P PSR 1 1 1 P U P P 0 0 P 1 1 **P DC U P P U P P P51 U P P P61 U P P P71 U P P P81 U P
Bit 0
P C90 1 1 P PSR 0 1 1 P U P P 0 0 P 1 1 **P C U P P U P P P50 U P P P60 U P P P70 U P P P80 U P
N/A
IOC9
N/A
CONT
0x00
R0(IAR)
0x01
R1(TCC)
0x02
R2(PC)
0x03
R3(SR)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
0x04
R4(RSR)
0x05
R5(P5)
0x06
R6(P6)
0x07
R7(P7)
0x08
R8(P8)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT
34 *
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
Address
Name
Reset Type Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
Bit 7
P P97 U P P SRB 7 U P P SWB 7 U P P ENS DO 0 0 P CES 0 0 P TMR 17 0 0 P PWP 7 1 1 P U U U 0 0 P S7 1 1
Bit 6
P P96 U P P SRB 6 U P P SWB 6 U P P OBD C 0 0 P SPIE 0 0 P TMR 16 0 0 P PWP 6 1 1 P U U U 0 0 P 1 1
Bit 5
P P95 U P P SRB 5 U P P SWB 5 U P P IBDC 0 0 P SRO 0 0 P TMR 15 0 0 P PWP 5 1 1 P U U U 0 0 P 1 1
Bit 4
P P94 U P P SRB 4 U P P SWB 4 U P P TIIF 0 0 P SPIS E 0 0 P TMR 14 0 0 P PWP 4 1 1 P U U U 0 0 P 1 1
Bit 3
P P93 U P P SRB 3 U P P SWB 3 U P P OD3 0 0 P 0 0 P TMR 13 0 0 P PWP 3 1 1 P T1IF 0 0 P 0 0 P /PU9 1 1
Bit 2
P P92 U P P SRB 2 U P P SWB 2 U P P OD4 0 0 P SBR S2 0 0 P TMR 12 0 0 P PWP 2 1 1 P SPIIF 0 0 P T1E 0 0 P /PU8 1 1
Bit 1
P P91 U P P SRB 1 U P P SWB 1 U P P RBFI F 0 0 P SBR S1 0 0 P TMR 11 0 0 P PWP 1 1 1 P EXIF 0 0 P T1P1 0 0 P /PU6 1 1
Bit 0
P P90 U P P SRB 0 U P P SWB 0 U P P RBF 0 0 P SBR S0 0 0 P TMR 10 0 0 P PWP 0 1 1 P TCIF 0 0 P T1P0 0 0 P /PU5 1 1
0x09
R9(P9)
0x0A
RA(SPIRB)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
0x0B
RB(SPIWB)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
0x0C
RC(SPIS)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
0x0D
RD(SPIC)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
0x0E
RE(TMR1)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
0x0F
RF(PWP)
0x3F
R3F(ISR)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
0x0C
IOCC
0x0D
IOCD
Power-On /RESET and WDT
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
* 35
EM78P451S
8-Bit Microcontroller with OTP ROM
Address
Name
Reset Type Wake-Up from Pin Change Bit Name
Bit 7
P U U U U U U U P P
Bit 6
P ODE 0 0 P U U U U P P
Bit 5
P WTE 1 1 1 U U U U P P
Bit 4
P SLP C 1 1 1 U U U U P P
Bit 3
P ROC 0 0 P T1IE 0 0 P U P P
Bit 2
P U U U SPII E 0 0 P U P P
Bit 1
P U U U EXIE 0 0 P U P P
Bit 0
P /WU E 1 1 P TCIE 0 0 P U P P
0x0E
IOCE
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
0x0F
IOCF
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
0x10~0x3E
GPR
Power-On /RESET and WDT Wake-Up from Pin Change
** To execute the next instruction after the "SLPC" bit status of IOCE register being on high-to-low transition.
X: NOTE used. U: Unknown or don't care. -: Not defined P: Previous value before reset. t: Check Table 7
The Status of RST, T, and P of STATUS Register A RESET condition is initiated by the following events: 1. A power-on condition, 2. Watchdog timer time-out. The values of T and P, listed in Table 7 are used to check how the processor wakes up. Table 8 shows the events that may affect the status of T and P. Table 8 The Values of RST, T and P After RESET
Reset Type Power on WDT during Operating mode WDT wake-up during SLEEP1 mode WDT wake-up during SLEEP2 mode Wake-Up on pin change during SLEEP2 mode T 1 0 0 0 P P 1 P 0 P P
* P: Previous value before reset
36 *
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM Table 9 The Status of RST, T and P Being Affected by Events
Event Power on WDTC instruction WDT time-out SLEP instruction Wake-Up on pin change during SLEEP2 mode T 1 1 0 1 P P 1 1 *P 0 P
* P: Previous value before reset
4.8 Interrupt
The EM78P451S has the following interrupts. 1. /TCC overflow interrupt 2. External interrupt (/INT) 3. Serial Peripheral Interface (SPI) transmission completed interrupt. 4. Timer1 comparator completed interrupt. R3F is the interrupt status register, which records the interrupt request in flag bit. IOCF is the interrupt mask register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (if enabled) is generated, will cause the next instruction to be fetched from address 001H. Once in the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the R3F register. The interrupt flag bit must be cleared by software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. The flag in the Interrupt Status Register (R3F) is set regardless of the status of its mask bit or the execution of ENI instruction. Note that reading R3F will obtain the output of logic AND of R3F and IOCF (refer to Fig. 17). The RETI instruction exits interrupt routine and enables the global interrupt (execution of ENI instruction). When an interrupt is generated by INT instruction (if enabled), it causes the next instruction to be fetched from address 002H.
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
* 37
EM78P451S
8-Bit Microcontroller with OTP ROM
/IRQn
PQ R CLK C LQ R3F D
IRQn IRQm RFRD ENI/DISI interrupt
QP D R C CLK QL
IOD IOCFWR
RESET
IOCF
IOCFRD
RFWR
Fig. 17 Interrupt Input Circuit
4.9 Oscillator
4.9.1 Oscillator Modes
The EM78P451S can operate in four different oscillator modes. There are high XTAL (HXT) oscillator mode, low XTAL (LXT) oscillator mode, External RC oscillator mode (ERC), and Internal C External R oscillator modes. User can select one of them by programming MS, RCT, HLF and HLP in the Code Option Register. Table 9 depicts how these three modes are defined. Table 10 Oscillator Modes by MS, IRC, RCT.
Mode High XTAL Oscillator Low XTAL Oscillator External RC Oscillator External R and Internal C Oscillator MS 1 1 0 0 RCT X X 1 0 HLF 1 0 X X HLP X 0 X X
X: Don't care
4.9.2 Crystal Oscillator/Ceramic Resonators (XTAL)
EM78P451S can be driven by an external clock signal through the OSCI pin as shown in Fig 18 below. In the most applications, pin OSCI and pin OSCO is connected with a crystal or ceramic resonator to generate oscillation. Fig 19 depicts such circuit. Table 10 provides the recommended values of C1 and C2. Since each resonator has its own attribute, user should refer to its specification for appropriate values of C1 and C2. RS, a serial resistor may be necessary for AT strip cut crystal or low frequency mode.
38 * Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
OSCI OSCO EM78P451S
Ext. Clock
Fig. 18 Circuit for External Clock Input
C1 OSCI XTAL
EM 78P451S OSCO
RS
C2
Fig. 19 Circuit for Crystal/Resonator Table 11 Capacitor Selection Guide for Crystal Oscillator Ceramic Resonators
Oscillator Type Frequency Mode Frequency 455 KHz Ceramic Resonator HXT 1.0 MHz 2.0 MHz 4.0 MHz 32.768 KHz LXT Crystal Oscillator HXT 100 KHz 200 KHz 455 KHz 1.0 MHz 2.0 MHz 4.0 MHz C1 (pF) 10~150 40~80 20~40 10~30 25 25 25 20~40 15~30 15 15 C2 (pF) 10~150 40~80 20~40 10~30 15 25 25 20~150 15~30 15 15
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
* 39
EM78P451S
8-Bit Microcontroller with OTP ROM
4.9.3 RC Oscillator Mode
For some applications that do not need a very precise timing calculation, the RC oscillator (Fig 22 & Fig 23) offers a lot of cost savings. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to the manufacturing process variation. In order to maintain a stable system frequency, the values of the Cext should not be less than 20pF, and that the value of Rext should not be greater than 1 M ohm. If they cannot be kept in this range, the frequency is easily affected by noise, humidity, and leakage. The smaller the Rext in the RC oscillator, the faster its frequency will be. On the contrary, for very low Rext values, for instance, 1 K, the oscillator becomes unstable because the NMOS cannot discharge the current of the capacitance correctly. Based on the reasons above, it must be kept in mind that all of the supply voltage, the operation temperature, the components of the RC oscillator, the package types, the way the PCB is layout, will affect the system frequency.
Vcc Rext
OSCI Cext EM 78P451S
Fig. 20 Circuit for External RC Oscillator Mode
Vcc Rext
OSCI EM 78P451S
Fig. 21 Circuit for External R, Internal C Oscillator Mode
40 *
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM Calibrate frequency of External RC oscillator (For reference only)
C ext R ext 3.3K 5.1K 10K 100K 3.3K 100pF 5.1K 10K 100K 3.3K 5.1K 10K 100K Fosc @5.0V,25 3.4MHz 2.2MHz 1.3MHz 144KHz 1.2MHz 935KHz 420KHz 45KHz 550KHz 360KHz 190KHz 28KHz
20pF
300pF
Internal C, external R Table (For reference only)
External R (Ohm) 10K 15K 20K 30K 51K 100K 150K 200K 510K 2M 3.3M Fosc @5.0V, 25 12M 7.7M 5.7M 3.65M 2.24M 1.14M 749K 559K 214K 56K 32.8K (Hz)
4.10 Code Option Register
WORD 0
12
MS
11
10
9
PTB
8
HLF
7
RCT
6
HLP
5
DEL1
4
DEL0
3
REN
2
N/A
1
N/A
0
N/A
ENWD CLKS T
Bit 12 (MS): Oscillator type selection. 0: RC type 1: XTAL type Bit 11 (ENWDT): Watchdog Timer enabled. 0: Enable 1: Disable Bit 10 (CLKS): Clocks of each instruction cycle. 0: Two clocks 1: Four clocks
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
* 41
EM78P451S
8-Bit Microcontroller with OTP ROM Bit 9 (PTB): Protect bit. 0: Protect enabled 1: Protect disabled Bit 8 (HLF): XTAL frequency selection. 0: Low frequency (32.768KHz) 1: High frequency This bit is useful only when Bit 12 (MS) is 1. When MS is 0, HLF must be 0. Bit 7 (RCT): Resistor Capacitor. 0: internal RC 1: external RC Bit 6 (HLP): Power consumption selection. 0: Low power 1: High power Bit 5 ~ Bit 4: DEL1 and DEL0 (SDI) input delay time options.
DEL 1 1 0 1 DEL 0 1 1 0 Delay time 0 ns 50 ns 100 ns
Bit3~0 (REN): reset pin enable bit 0: enable, P70/reset=>reset pin 1: disable, P70/reset=> P70 WORD 1 ( user's ID code)
12
ID12
11
ID11
10
ID10
9
ID9
8
ID8
7
ID7
6
ID6
5
ID5
4
ID4
3
ID3
2
ID2
1
ID1
0
ID0
4.11 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. All instructions are executed within one single instruction cycle (consisting of 2 oscillator periods), unless the program counter is changed by(a) Executing the instruction "MOV R2,A", "ADD R2,A", "TBL", or any other instructions that write to R2 (e.g. "SUB R2,A", "BS R2,6", "CLR R2", ). (b) execute CALL, RET, RETI, RETL, JMP, Conditional skip (JBS, JBC, JZ, JZA, DJZ, DJZA) which were tested to be true. Under these cases, the execution takes two instruction cycles. In addition, the instruction set has the following features:
42 * Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM (1). Every bit of any register can be set, cleared, or tested directly. (2). The I/O register can be regarded as general register. That is, the same instruction can operate on I/O register. The symbol "R" represents a register designator that specifies which one of the registers (including operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b" represents a bit field designator that selects the value for the bit located in the register "R" and affects operation. "k" represents an 8 or 10-bit constant or literal value.
INSTRUCTION BINARY 0 0000 0000 0000 0 0000 0000 0001 0 0000 0000 0010 0 0000 0000 0011 0 0000 0000 0100 0 0000 0000 rrrr 0 0000 0001 0000 0 0000 0001 0001 0 0000 0001 0010 0 0000 0001 0011 0 0000 0001 0100 0 0000 0001 rrrr 0 0000 0010 0000 0 0000 01rr rrrr 0 0000 1000 0000 0 0000 11rr rrrr 0 0001 00rr rrrr 0 0001 01rr rrrr 0 0001 10rr rrrr 0 0001 11rr rrrr 0 0010 00rr rrrr 0 0010 01rr rrrr 0 0010 10rr rrrr 0 0010 11rr rrrr 0 0011 00rr rrrr 0 0011 01rr rrrr 0 0011 10rr rrrr 0 0011 11rr rrrr 0 0100 00rr rrrr 0 0100 01rr rrrr 0 0100 10rr rrrr
HEX 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 0020 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr
MNEMONIC NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R TBL MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R
OPERATION No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC, Enable Interrupt CONT A IOCR A R2+A R2, Bits 8~9 of R2 unchanged AR 0A 0R R-A A R-A R R-1 A R-1 R A VR A A VR R A&RA A&RR ARA ARR A+RA A+RR RA RR /R A
STATUS AFFECTED None C None T,P T,P None None None None None None None Z,C,DC None Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z * 43
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
INSTRUCTION BINARY 0 0100 11rr rrrr 0 0101 00rr rrrr 0 0101 01rr rrrr 0 0101 10rr rrrr 0 0101 11rr rrrr 0 0110 00rr rrrr 0 0110 01rr rrrr 0 0110 10rr rrrr 0 0110 11rr rrrr 0 0111 00rr rrrr 0 0111 01rr rrrr 0 0111 10rr rrrr 0 0111 11rr rrrr 0 100b bbrr rrrr 0 101b bbrr rrrr 0 110b bbrr rrrr 0 111b bbrr rrrr 1 00kk kkkk kkkk 1 01kk kkkk kkkk 1 1000 kkkk kkkk 1 1001 kkkk kkkk 1 1010 kkkk kkkk 1 1011 kkkk kkkk 1 1100 kkkk kkkk 1 1101 kkkk kkkk 1 1110 0000 0010 1 1111 kkkk kkkk HEX 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E02 1Fkk MNEMONIC COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT ADD A,k OPERATION /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1), R(0) C, C A(7) R(n) R(n-1), R(0) C, C R(7) R(n) A(n+1), R(7) C, C A(0) R(n) R(n+1), R(7) C, C R(0) R(0-3) A(4-7), R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP], (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A PC+1 [SP], 002H PC k+A A STATUS AFFECTED Z Z Z None None C C C C None None None None None None None None None None None Z Z Z None Z,C,DC None Z,C,DC
NOTE This instruction is applicable to IOC5 ~ IOC9, IOCD~IOCF only. This instruction is not recommended for RF operation. This instruction cannot operate on R3F.
44 *
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
4.12 Timing Diagrams
AC Test Input/Output Waveform
2.4 2.0 0.8 0.4
TEST POINTS
2.0 0.8
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are made at 2.0V for logic "1",and 0.8V for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1 Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins CLK
TCC
Ttcc
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
* 45
EM78P451S
8-Bit Microcontroller with OTP ROM
5
ABSOLUTE MAXIMUM RATING
Items Rating 0C -65C -0.3V -0.3V DC to to to to to 70C 150C +6.0V +6.0V 20MHz
Temperature under bias Storage temperature Input voltage Output voltage Operating Frequency (2clk)
6
ELECTRICAL CHARACTERISTICS
6.1 DC Characteristic
(Ta=25C, VDD=5V5%, VSS=0V)
Symbol FXT Parameter XTAL VDD to 2.3V XTAL VDD to 3V XTAL VDD to 5V RC VDD to 2.3V RC VDD to 3V RC VDD to 5V Input Leakage Current Input High Voltage VDD=5V) Input Low Voltage (VDD=5V) Clock Input High Voltage (VDD=5V) Clock Input Low Voltage (VDD=5V) Input high threshold voltage (Schmitt trigger) Input low threshold voltage (Schmitt trigger) Input High Voltage(VDD=3V) Input Low Voltage (VDD=3V) Clock Input High Voltage (VDD=3V) Clock Input Low Voltage (VDD=3V) Output High Voltage (Ports 5,6,8, P74~P77, P90~P92,P95~P97,) Output High Voltage (P70~P72) Condition Two clocks Min DC DC DC DC DC DC Typ Max 4 8 20 4 4 4 1 2.0 0.8 OSCI OSCI P70/RESET pin P70/RESET pin 1.5 0.4 OSCI OSCI IOH = -12.0mA S7=1(IOCD Register bit7), IOH = -9.0mA S7=0(IOCD Register bit7), IOH = -12.0mA 2.4 2 2.4 2.4 V 1.5 0.6 2.0 0.8 2.5 1.0 Unit MHz
FRC IIL VIH1 VIL1 VIHX1 VILX1 VIHT1 VILT1 VIH2 VIL2 VIHX2 VILX2 VOH1
Two clocks VIN = VDD, VSS
MHz A V V V V V V V V V V V
VOH2
46 *
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
Symbol VOH3
VOL1
Parameter Output High Voltage (P93/SDO,P94/SCK) Output Low Voltage (Ports 5,6,8, P74~P77, P90~P92,P95~P97)) Output Low Voltage (P70~P72) Output Low Voltage (P93/SDO, P94/SCK) Output Low Voltage (P74~P77) Pull-high current Pull-high current (P74,P75) Pull high current (P70/RESET) Power down current Operating supply current
Condition IOH = -12.0mA IOL =12.0mA S7=1(IOCD Register bit7), IOH = 9.0mA S7=0(IOCD Register bit7), IOH = 12.0mA IOL = 12.0mA IOL = 15.0mA Pull-high active, input pin at VSS Pull-high active, input pin at VSS Pull-high active, input pin at VSS All input and I/O pin at VDD, output pin floating, WDT enabled /RESET="High", Fosc=1.84324MHz (CK2="0"), output pin floating
Min 2.4
Typ
Max
Unit V
0.4 0.4 0.8
V
VOL2
V 0.4 0.4 0.4 -50 -100 1 -16 -22 -29 10 3 -240 A mA A A mA V
VOL3 VOL4 IPH IPH2 IPH3 ISB ICC
6.2 AC Characteristic
(Ta=0C~70C, VDD=5V5%, VSS=0V)
Symbol Dclk Tins Ttcc Twdt Tdrh Parameter Input CLK duty cycle Instruction cycle time (CK2="0") TCC input period Watchdog timer period Device reset hold period Ta=25C Ta=25C RC Type Conditions Min 45 500 (Tins+20)/N* 18 183 Typ 50 Max 55 DC Unit % ns ns ms ms
N= selected prescaler ratio.
3
NOTE: Vdd = 5V, set up time period = 16.2ms 30% Vdd = 3V, set up time period = 18.0ms 30%
* 47
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
7
Application Circuit
EM78P451S
48 *
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
APPENDIX A Package Types
OTP MCU EM78P451SP EM78P451SWM EM78P451SAQ Package Type DIP SOP QFP Pin Count 40 40 44 Package Size 600 mil 450 mil
B Package Information
40-Lead Plastic Dual in line (PDIP) 600 mil
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
* 49
EM78P451S
8-Bit Microcontroller with OTP ROM 44--Lead Quad flat package (QFP)
50 *
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)

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